1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device allowing reduction of an area loss in a power supply circuit, which generates an internal voltage within the semiconductor memory device.
2. Description of the Background Art
Owing to advances in semiconductor technology, it is now possible to produce a logic-mixed memory, which includes a logic circuit and a DRAM (Dynamic Random Access Memory) in a single chip. This can significantly improve a data transfer rate between the logic circuit and the DRAM.
Referring to FIG. 34, a logic-mixed memory 700 includes a DRAM 800, SRAMs (Static Random Access Memories) 810 and 820, a logic circuit 830 and pads 840.
DRAM 800 and SRAMs 810 and 820 are memories for storing data. Logic circuit 830 controls input/output of data to and from DRAM 800 and SRAMs 810 and 820. Pads 840 are terminals and are arranged in a peripheral portion for inputting and/or outputting a power supply voltage, control signals and data to and/or from logic-mixed memory 700.
In logic-mixed memory 700, logic circuit 830 rapidly transmits data and others to and from the memories, i.e., DRAM 800 and SRAMs 810 and 820.
Referring to FIG. 35, DRAM 800 includes memory cell arrays 801 and 802, a row column decoder 803, data buses 804 and 805, a control circuit 806, a power supply circuit 807 and a test circuit 808.
Each of memory cell arrays 801 and 802 includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of sense amplifiers provided corresponding to the respective bit line pairs, a plurality of equalize circuits provided corresponding to the respective bit line pairs, and others. The plurality of memory cells are arranged in rows and columns. The plurality of word lines are arranged in the row directions of the plurality of memory cells arranged in rows and columns. The plurality of bit line pairs are arranged in the column direction of the plurality of memory cells arranged in rows and columns.
Row column decoder 803 is arranged between memory cell arrays 801 and 802. Row column decoder 803 decodes an externally applied address, and activates the word line or the bit line pair designated by the decoded address.
Data buses 804 and 805 are lines for transmitting the data to and from the plurality of memory cells included in memory cell arrays 801 and 802. Control circuit 806 controls operations such as input/output of data with respect to the plurality of memory cells.
Power supply circuit 807 generates an internal voltage based on an external power supply voltage, which is externally supplied, and supplies the internal voltage thus generated to memory cell arrays 801 and 802 as well as peripheral circuits such as control circuit 806.
Test circuit 808 conducts tests on DRAM 800.
Referring to FIG. 36, power supply circuit 807 includes a Vbb generating circuit 850, a reference voltage generating circuit 860, a voltage down converter 870, Vcc/2 generating circuits 880 and 890, and a VPP generating circuit 900.
Vbb generating circuit 850 is formed of a level converter 851, a control circuit 852, a detecting circuit 853, an oscillator 854 and a pump circuit 855. Level converter 851 receives power supply voltages from nodes N1 and N2. Node N1 supplies the power supply voltage, e.g., of 1.5 V. Node N2 supplies the power supply voltage, e.g., of 3.3 V. Level converter 851 receives a control signal such as a test mode signal TM, and converts the voltage level forming test mode signal TM thus received from 1.5 V to 3.3 V. Level converter 851 provides test mode signal TM subjected to the level conversion to control circuit 852.
Control circuit 852 receives the power supply voltage of 3.3 V from node N2. Control circuit 852 controls detecting circuit 853 based on test mode signal TM received from level converter 851. More specifically, when test mode signal TM is at an H (logical high) level, control circuit 852 activates or deactivates detecting circuit 853 for conducting various tests. When test mode signal TM is at an L (logical low) level, control circuit 852 activates detecting circuit 853.
Detecting circuit 853 receives the power supply voltage of 3.3 V from node N2. Detecting circuit 853 detects a negative voltage Vbb when a signal BIASL received from a current source 861 of reference voltage generating circuit 860 is at H-level, and provides the detection signal of negative voltage Vbb to oscillator 854.
Oscillator 854 receives the power supply voltage of 3.3 V from node N2. Oscillator 854 generates a clock CLK, which has a phase corresponding to the logical level of the detection signal received from detecting circuit 853, and provides clock CLK thus generated to pump circuit 855.
Pump circuit 855 receives a power supply voltage of 3.3 V from node N2. Pump circuit 855 pumps carriers to generate negative voltage Vbb of 0.7 V in synchronization with clock CLK received from oscillator 854.
As described above, Vbb generating circuit 850 is driven by the power supply voltage of 3.3 V received from node N2, and generates negative voltage Vbb of xe2x88x920.7 V for providing it to memory cell arrays 801 and 802.
Reference voltage generating circuit 860 includes current source 861 and a voltage generating circuit 862. Current source 861 receives the power supply voltage of 3.3 V from node N2. Based on the power supply voltage of 3.3 V received from node N2, current source 861 generates a voltage VII as well as signals BIASL and ICONST formed of a voltage in a linear operation region of the MOS transistor, provides voltage VII and signal ICONST thus generated to voltage generating circuit 862, and provides signal BIASL to detecting circuit 853 of Vbb generating circuit 850, voltage down converter 870 and VPP generating circuit 900. Signal ICONST is formed of a maximum voltage in the linear motion region of the MOS transistor. Signal BIASL is formed of a minimum voltage in the linear motion region of the MOS transistor.
Voltage generating circuit 862 receives voltage VII and signal ICONST from current source 861, and operates based on voltage VII and signal ICONST thus received to generate a reference voltage VrefS of 1.5 V and provide it to voltage down converter 870 and VPP generating circuit 900.
As described above, reference voltage generating circuit 860 is driven by the power supply voltage of 3.3 V received from node N2, and generates reference voltage VrefS of 1.5 V lower than the power supply voltage.
Voltage down converter 870 includes a level converter 871, a control circuit 872, differential amplifier circuits 873 and 876, P-channel MOS transistors 874 and 877, and N-channel MOS transistors 875 and 878. Level converter 871 receives the power supply voltage of 1.5 V from node N1, and receives the power supply voltage of 3.3 V from node N2. Level converter 871 receives control signals such as test mode signal TM, sense amplifier enable signal SAE or the like, and converts the voltage level of received test mode signal TM or sense amplifier enable signal SAE from 1.5 V to 3.3 V. Level converter 871 provides test mode signal TM or sense amplifier enable signal SAE at the converted level to control circuit 872.
Control circuit 872 receives the power supply voltage of 3.3 V from node N2. Control circuit 872 receives test mode signal TM or sense amplifier enable signal SAE from level converter 871, and provides received test mode signal TM or sense amplifier enable signal SAE to a gate terminal of N-channel MOS transistor 875. In the test mode of DRAM 800, control circuit 872 receives test mode signal TM at H- or L-level corresponding to contents of the intended test, and provides received test mode signal TM at H- or L-level to the gate terminal of N-channel MOS transistor 875. In the normal operation of DRAM 800, control circuit 872 receives sense amplifier enable signal SAE at H-level, and provides received sense amplifier enable signal SAE at H-level to the gate terminal of N-channel MOS transistor 875. During standby of DRAM 800, control circuit 872 receives sense amplifier enable signal SAE at L-level, and provides received sense amplifier enable signal SAE at L-level to the gate terminal of N-channel MOS transistor 875.
Differential amplifier circuit 873 is connected between node N2 and N-channel MOS transistor 875, receives reference voltage VrefS sent from reference voltage generating circuit 860 on its noninverting input terminal, and receives on its inverting input terminal an array voltage VccS carried on an output node NOUT. When N-channel MOS transistor 875 receives test mode signal TM at H-level or sense amplifier enable signal SAE at H-level on its gate terminal, differential amplifier circuit 873 is activated. When N-channel MOS transistor 875 receives test mode signal TM at L-level or sense amplifier enable signal SAE at L-level on its gate terminal, differential amplifier circuit 873 is deactivated.
When differential amplifier circuit 873 is activated, it differentially amplifies array voltage VccS so that array voltage VccS may attain the voltage level of reference voltage VrefS, and provides the amplified voltage of 1.5 V to the gate terminal of P-channel MOS transistor 874. When differential amplifier circuit 873 is deactivated, it provides a voltage, which is close to the power supply voltage of 3.3 V received from node N2, to the gate terminal of P-channel MOS transistor 874.
P-channel MOS transistor 874 is connected between node N2 and output node NOUT. P-channel MOS transistor 874 supplies carriers from node N2 to output node NOUT in accordance with the voltage received from differential amplifier circuit 873.
N-channel MOS transistor 875 is connected between differential amplifier circuit 873 and a ground node NS1, and receives test mode signal TM or sense amplifier enable signal SAE from control circuit 872 on its gate terminal.
Differential amplifier circuit 876 is connected between node N2 and N-channel MOS transistor 878, receives reference voltage VrefS from reference voltage generating circuit 860 on its noninverting input terminal, and receives, on its inverting input terminal, array voltage VccS carried on output node NOUT. Differential amplifier circuit 876 is activated when N-channel MOS transistor 878 receives signal BIASL at H-level from current source 861 of reference voltage generating circuit 860, and is deactivated when it receives signal BIASL at L-level. When activated, differential amplifier circuit 876 differentially amplifies array voltage VccS so that array voltage VccS may attain the voltage level of reference voltage VrefS, and provides the amplified voltage of 1.5 V to the gate terminal of P-channel MOS transistor 877.
P-channel MOS transistor 877 is connected between node N2 and output node NOUT. P-channel MOS transistor 877 supplies carriers from node N2 to output node NOUT in accordance with the voltage received from differential amplifier circuit 876.
N-channel MOS transistor 878 is connected between differential amplifier circuit 876 and ground node NS1, and receives signal BIASL sent from current source 861 of reference voltage generating circuit 860 on its gate terminal.
When N-channel MOS transistor 875 receives test mode signal TM at H-level or sense amplifier enable signal SAE at H-level on its gate terminal, differential amplifier circuit 873 is activated so that it differentially amplifies array voltage VccS to attain the voltage level of reference voltage VrefS, and provides the amplified voltage of 1.5 V to the gate terminal of P-channel MOS transistor 874. P-channel MOS transistor 874 supplies carriers from node N2 to output node NOUT in accordance with the voltage of 1.5 V received from differential amplifier circuit 873, and thereby sets voltage VccS on output node NOUT to 1.5 V. When differential amplifier circuit 873 is inactive, P-channel MOS transistor 874 receives a voltage close to 3.3 V on its gate terminal so that it is substantially turned off, and the voltage level of array voltage VccS on output node NOUT lowers.
When N-channel MOS transistor 878 receives signal BIASL at H-level on its gate terminal, differential amplifier circuit 876 and P-channel MOS transistor 877 perform the same operations as differential amplifier circuit 873 and P-channel MOS transistor 874, respectively, so that array voltage VccS on output node NOUT is set to 1.5 V. When N-channel MOS transistor 878 receives signal BIASL at L-level and differential amplifier circuit 876 is deactivated, the voltage level of array voltage VccS on output node NOUT lowers similarly to the case when differential amplifier circuit 873 is deactivated.
When DRAM 800 in on standby, N-channel MOS transistor 875 receives sense amplifier enable signal SAE at L-level on its gate terminal, and N-channel MOS transistor 878 receives signal BIASL formed of a voltage level of 0.7 V on its gate terminal. Consequently, differential amplifier circuit 873 is deactivated, and differential amplifier circuit 876 is activated.
Thereby, differential amplifier circuit 876 differentially amplifies array voltage VccS on output node NOUT so that array voltage VccS may attain the voltage level of reference voltage VrefS, and provides the amplified voltage to the gate terminal of P-channel MOS transistor 877. P-channel MOS transistor 877 supplies carriers from node N2 to output node NOUT in accordance with the voltage received from differential amplifier circuit 876.
Accordingly, differential amplifier circuit 876 as well as P- and N-channel MOS transistors 877 and 878 lower the power supply voltage of 3.3 V to generate array voltage VccS of 1.5 V when DRAM 800 is on standby. In this case, N-channel MOS transistor 878 receives signal BIASL formed of the voltage level of 0.7 V on its gate terminal, and therefore has a channel width smaller than that in the normal operation. Accordingly, a current flowing through differential amplifier circuit 876 is smaller than that in the normal operation, and differential amplifier circuit 876 provides a voltage at a higher level than that in the normal operation to P-channel MOS transistor 877. Thereby, P-channel MOS transistor 877 supplies carriers smaller in amount than those in the normal operation from node N2 to output node NOUT so that array voltage VccS attains the voltage level of 1.5 V more slowly than that in the normal operation.
In the normal operation of DRAM 800, N-channel MOS transistor 875 receives sense amplifier enable signal SAE at H-level on its gate terminal, and N-channel MOS transistor 878 receives signal BIASL formed of the voltage level of 0.7 V on its gate terminal. Thereby, differential amplifier circuits 873 and 876 are activated. In this case, sense amplifier enable signal SAE at H-level is formed of a voltage level of 3.3 V so that the channel width of N-channel MOS transistor 875 is wider than that of N-channel MOS transistor 878. Therefore, the current flowing through differential amplifier circuit 873 is larger than the current flowing through differential amplifier circuit 876, and differential amplifier circuit 873 provides a voltage lower than that of differential amplifier circuit 876 to P-channel MOS transistor 874. Consequently, P-channel MOS transistor 874 supplies more carriers than P-channel MOS transistor 877 from node N2 to output node NOUT.
In the normal operation of DRAM 800, therefore, differential amplifier circuit 873, P-channel MOS transistor 874 and N-channel MOS transistor 875 set the voltage level of array voltage VccS to 1.5 V more rapidly than differential amplifier circuit 876, P-channel MOS transistor 877 and N-channel MOS transistor 878.
In the normal operation of DRAM 800, as described above, differential amplifier circuit 873, P-channel MOS transistor 874 and N-channel MOS transistor 875 lower the power supply voltage of 3.3 V to set rapidly the voltage level of array voltage VccS to 1.5 V. During standby of DRAM 800, differential amplifier circuit 876, P-channel MOS transistor 877 and N-channel MOS transistor 878 lower the power supply voltage of 3.3 V to set slowly the voltage level of array voltage VccS to 1.5 V.
The number of circuits each formed of differential amplifier circuit 873 and P- and N-channel MOS transistors 874 and 875 as well as the number of circuits each formed of differential amplifier circuit 876 and P- and N-channel MOS transistors 877 and 878 are variable depending on the number of blocks forming memory cell arrays 801 and 802.
As described above, voltage down converter 870 is driven by the power supply voltage of 3.3 V. In the normal operation of DRAM 800, voltage down converter 870 lowers the power supply voltage of 3.3 V to supply rapidly array voltage VccS of 1.5 V to output node NOUT. During standby of DRAM 800, voltage down converter 870 lowers the power supply voltage of 3.3 V to supply slowly array voltage VccS of 1.5 V to output node NOUT.
Vcc/2 generating circuit 880 is driven by the power supply voltage of 3.3 V received from node N2. Vcc/2 generating circuit 880 receives array voltage VccS on output node NOUT, and halves array voltage VccS to generate a precharge voltage VBL. Vcc/2 generating circuit 890 is driven by the power supply voltage of 3.3 V received from node N2. Vcc/2 generating circuit 890 receives array voltage VccS on output node NOUT, and halves array voltage VccS to generate a cell plate voltage VCP.
VPP generating circuit 900 includes a level converter 901, a control circuit 902, a dividing circuit 903, detecting circuits 904 and 905, an oscillator 906 and pump circuits 907-910.
Level converter 901 receives the power supply voltage of 1.5 V from node N1, and receives the power supply voltage of 3.3 V from node N2. Level converter 901 receives test mode signal TM or a row address strobe signal RAS, and converts the voltage level of received test mode signal TM or row address strobe signal RAS from 1.5 V to 3.3 V for providing it to control circuit 902.
Control circuit 902 receives the power supply voltage of 3.3 V from node N2. Control circuit 902 provides test mode signal TM or row address strobe signal RAS received from level converter 901 to detecting circuits 904 and 905. In the test mode of DRAM 800, control circuit 902 receives test mode signal TM at H- or L-level depending on contents of the test, and provides received test mode signal TM at H- or L-level to detecting circuits 904 and 905. In the normal operation of DRAM 800, control circuit 902 receives row address strobe signal RAS at H-level, and provides received row address strobe signal RAS at H-level to detecting circuit 904. During standby of DRAM 800, control circuit 902 receives row address strobe signal RAS at L-level, and provides received row address strobe signal RAS to detecting circuit 904.
Dividing circuit 903 divides boosted voltage VPP of 3.3 V to provide a divided voltage VDIV of 1.5 V to detecting circuits 904 and 905. Detecting circuit 904 receives the power supply voltage of 3.3 V from node N2. Detecting circuit 904 is activated by row address strobe signal RAS at H-level received from control circuit 902, and differentially amplifies divided voltage VDIV so that divided voltage VDIV provided from dividing circuit 903 may match with reference voltage VrefS received from reference voltage generating circuit 860. Thus, detecting circuit 904 detects divided voltage VDIV, and provides it to oscillator 906.
Detecting circuit 905 receives the power supply voltage of 3.3 V from node N2. Detecting circuit 905 is activated by signal BIASL sent from current source 861 of reference voltage generating circuit 860, and differentially amplifies divided voltage VDIV received from dividing circuit 903 so that divided voltage VDIV may match with reference voltage VrefS received from reference voltage generating circuit 860. Thus, detecting circuit 905 detects divided voltage VDIV, and provides it to oscillator 906.
Row address strobe signal RAS at H-level is formed of a voltage level of 3.3 V, and signal BIASL is formed of a voltage level of 0.7 V. Therefore, detecting circuit 904 detects divided voltage VDIV more rapidly than detecting circuit 905, and provides it to oscillator 906.
In the normal operation of DRAM 800, detecting circuit 904 receives row address strobe signal RAS at H-level, and detecting circuit 905 receives signal BIASL. Therefore, detecting circuit 904 detects divided voltage VDIV more rapidly than detecting circuit 905, and provides it to oscillator 906. During standby of DRAM 800, detecting circuit 904 receives row address strobe signal RAS at L-level, and detecting circuit 905 receives signal BIASL formed of the voltage level of 0.7 V. Detecting circuit 904 is inactive, and detecting circuit 905 detects divided voltage VDIV more slowly than that in the normal operation, and provides it to oscillator 906. Therefore, detecting circuit 904 detects divided voltage VDIV in the normal operation, and detecting circuit 905 detects divided voltage VDIV during standby.
Oscillator 906 receives power supply voltage of 3.3 V from node N2. Oscillator 906 generates dock CLK having a phase corresponding to the voltage level of divided voltage VDIV received from detecting circuits 904 and 905, and provides clock CLK thus generated to pump circuits 907-910.
Each of pump circuits 907-910 receives the power supply voltage of 3.3 V from node N2. Each of pump circuits 907-910 pumps carriers in synchronization with clock CLK received from oscillator 906 to generate boosted voltage VPP. The number of pump circuits 907-910 is variable depending on the number of blocks forming memory cell arrays 801 and 802.
As described above, VPP generating circuit 900 is driven by the power supply voltage of 3.3 V, and boosts the power supply voltage of 3.3 V to generate boosted voltage VPP. As described above, power supply circuit 807 is driven by the power supply voltage of 3.3 V, and the MOS transistors forming Vbb generating circuit 850, reference voltage generating-circuit 860, voltage down converter 870, Vcc/2 generating circuits 880 and 890, and VPP generating circuit 900 have gate oxide films having a large thickness suitable to the drive voltage of 3.3 V.
However, control circuits 852, 872 and 902 as well as detecting circuits 853, 904 and 905, included in Vbb generating circuit 850, reference voltage generating circuit 860, voltage down converter 870, Vcc/2 generating circuits 880 and 890, and VPP generating circuit 900 are arranged adjacent to memory cell arrays 801 and 802, although they are not arranged in accordance with a pattern of repetition of the array circuits forming memory cell arrays 801 and 802 (see FIG. 35). Therefore, if the structures of memory cell arrays 801 and 802 are changed, the foregoing circuits cannot flexibly follow such changes. In particular, the control circuits are configured to form groups each having an independent or similar function, and this layout is determined in advance so each group corresponds to an integer multiple of the number into which memory cell arrays 801 and 802 are divided.
Accordingly, if memory cell arrays 801 and 802 have small capacities, an area loss occurs in arrangements of the respective circuits in power supply circuit 807.
More specifically, as shown in FIGS. 37-40, if a memory cell array has a capacity of 16 megabytes (Mb), the various circuits in the power supply circuit are arranged without an area loss (see FIG. 37). However, as the capacity of the memory cell array decreases to 4 Mb, 2 Mb and 1 Mb, an empty region increases so that the area loss increases (FIGS. 38-40).
If the arrangement of respective circuits in the power supply circuit is determined in accordance with the memory cell array having a small capacity, the area loss increases with an increase in the capacity of the memory cell array.
Accordingly, an object of the invention is to provide a semiconductor memory device provided with a power supply circuit, in which an area loss due to changes in capacity of a memory cell array is suppressed.
According to the invention, a semiconductor memory device includes a memory cell array storing data, a peripheral circuit inputting and outputting data to and from the memory cell array, and a power supply circuit supplying a power supply voltage to the memory cell array and the peripheral circuit. The power supply circuit is formed of a first power supply circuit group including voltage generating circuits of m (m: natural number) in number formed of thick film transistors having a first gate oxide film thickness, and each generating an internal voltage for inputting and outputting the data to and from the memory cell array, and a second power supply circuit group including voltage generating circuits of n (n: natural number) in number formed of thin film transistors having a second gate oxide film thickness smaller than the first gate oxide film thickness, and each generating an internal voltage. The first power supply circuit group corresponds to the memory cell array and is arranged in a first region neighboring to the memory cell array. The m voltage generating circuits are arranged in the first region to form units of m in number, and the second power supply circuit group is arranged in a second region other than the first region, and the n voltage generating circuits are arranged in the second region in a shuffled fashion.
According to the semiconductor memory device of the invention, the circuits formed of the thick film transistors having the first gate oxide film thickness are arranged to form units corresponding to the position of the memory cell array, and the circuits formed of the thin film transistors having the second gate oxide film thickness are arranged in a shuffled fashion.
In the invention, the thick film transistor represents an MOS transistor, which has a gate oxide film thickness suitable to a power supply voltage at a higher voltage level between two kinds of power supply voltages at different voltage levels. The thin film transistor represents an MOS transistor, which has a gate oxide film thickness suitable to the power supply voltage at a lower voltage level.
According to the invention, therefore, the circuits formed of the thick film transistors and the circuits formed of the thin film transistors can be arranged in a manner reducing the area loss even if changes occur in capacity of the memory cell array.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.